1. Field of Invention
The present invention relates to a dual damascene processing method. More particularly, the present invention relates to a dual damascene process that can be applied to form deeper vias and narrower metallic interconnects.
2. Description of Related Art
As the level of integration for integrated circuits increases, the number of interconnects necessary for linking up devices is going to increase too. Therefore, design employing two or more metallic layers is gradually becoming the norm in the fabrication of integrated circuits. When the level of integration is further increased a high production yield and good reliability is difficult to get. Damascene processing method is a fabrication technique that involves the creation of interconnect lines by first etching a trench in a planar dielectric layer, and then filling that trench with metal. The method is capable of producing highly reliable interconnects that also has a good yield. Therefore, this method is going to be the best selection in the manufacturing industry for sub-quarter micron interconnects.
Conventional damascene processing technique has a number of problems. For example, depth of trench lines is hard to control, profile of via sidewall is difficult to standardize, and the processing window is quite narrow.
FIG. 1A and FIG. 1B are cross-sectional views showing the manufacturing steps of a first conventional dual damascene processing method. As shown in FIG. 1A, a silicon dioxide layer 12 is deposited over a substrate 11. The substrate 11 has a desired wire-connecting region 10 (the desired wire-connecting region can be a metallic layer or a silicide layer) already formed thereon. Then, photolithographic and etching processes are carried out to form a via 13 that links up with the desired wire-connecting region 10. Next, reverse metal photolithographic and etching processes are performed to create trench lines 14 and 15. After the completion of etching, metal is deposited filling the via 13 and the trenches 14 and 15. Thereafter, unwanted metallic layer on the surface is removed using a chemical-mechanical polishing process, thereby forming the cross-sectional structure as shown in FIG. 1B.
In the above damascene method, the trenches and the via structures are formed within the same oxide layer. One big disadvantage is that, since there is no etching stop layer within the oxide layer, the oxide layer can be over-etched during trench etching operation. Furthermore, since trenches are etched using a reactive ion etching method, a rough bottom surface will be formed in the trenches. However, the biggest problem is that the depths of etch for the trenches are difficult to control, thereby leading to vastly different metal interconnect line thickness.
FIG. 2A and FIG. 2B are cross-sectional views showing the manufacturing steps of a second conventional dual damascene processing method. In this second double damascene method, a silicon nitride layer is formed in the middle of the oxide layer to act as an etching stop layer. Thus, unlike the first dual damascene method, the defect of over-etching due to the absence of a stop layer is prevented. First, as shown in FIG. 2A, a first oxide layer 23 is deposited over a substrate 22. The substrate 22 has a desired wire-connecting region 21 already formed thereon. Then, a silicon nitride layer 25 that has a via opening 24 is formed over the first oxide layer and established a structure as shown in FIG. 2A. Next, as shown in FIG. 2B, a second oxide layer 26 is deposited over the silicon nitride layer 25. This is followed by photolithographic and etching processes for forming the trenches. Due to the presence of a silicon nitride layer 25, after etching out trenches 27 and 28, etching will not continue down once the stop layer is reached. Only in places where a via opening 24 has formed in the silicon nitride layer 25, will the etching continues down until the desired wire-connecting region 21 is reached forming a via 29 as shown in FIG. 2B. Subsequently, metal is deposited filling the trenches 27, 28 and via 29 until they are completely filled. Thereafter, unwanted metal on the oxide surface is removed using a chemical-mechanical polishing method. Then, subsequent processes are carried out. Although this method can control the trench depth, there are some other problems too. The first problem is that the silicon nitride layer, which is used as a stop layer, has a rather large dielectric constant K, thereby increasing the parasitic capacitance of the interconnect lines. Furthermore, the etchant used in the etching must have a high silicon nitride/silicon dioxide selectivity ratio. Another problem is the narrow processing window. During photolithographic and etching operations, if the photomask is not properly aligned, the etching region will be shifted. The situation is depicted in FIG. 3. In FIG. 3, a substrate 31 having a desired wire-connecting region 30 already formed thereon is provided. Then, a first oxide layer 32, a silicon nitride layer 33 that has a via opening, and a second oxide layer 34 are sequentially formed over the substrate 31. Next, photolithographic and etching operations are performed. Width of the trench 35 remains unchanged. However, due to a moderate shift of photomask to the right, position of the etching region is correspondingly shifted thereby leading to a narrowing of the via 36. When metal is ultimately filled, contact area between the metal and the desired wire-connecting region will be reduced. A smaller contact area will increase the contact resistance between connecting wires. Therefore, this method has a narrow processing window and will increase the level of difficulty in processing.
In light of the foregoing, there is a need in the art to provide an improved dual damascene processing method.